A Pipelined Multi-core MIPS Machine
Mikhail Kovalev, Silvia M. Muller, Wolfgang J. Paul
Springer International Publishing AG, 2014
66,50 €On orderDelivery: 2-3 weeks
It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory.
- ISBN-13
- 9783319139050
- ISBN-10
- 3319139053
- Publisher
- Springer International Publishing AG
- Year
- 2014
- Publication date
- 2014-12-01
- Pages
- 352
- Dimensions
- 235x155x