Verilog and SystemVerilog Gotchas
Don Mills, Stuart Sutherland
Springer-Verlag New York Inc., 2007
197,25 €On orderDelivery: 2-3 weeks
This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages.
- ISBN-13
- 9780387717142
- ISBN-10
- 0387717145
- Publisher
- Springer-Verlag New York Inc.
- Year
- 2007
- Publication date
- 2007-06-26
- Pages
- 218
- Dimensions
- 164x241x22
- Weight
- 524